The present invention relates generally to semiconductor devices, and more particularly to dynamic random access memory (DRAM) storage cells and arrays.
A dynamic random access memory (DRAM) includes a large number of memory cells, each of which can store at least one bit of data. The memory cells are arranged in an array having a number of rows and columns. Memory cells within the same row are commonly coupled to a word line and memory cells within the same column are commonly coupled to a bit line. The memory cells within the array are accessed according to various memory device operations. Such operations include read operations, write operations and refresh operations.
In a typical memory cell read operation, an external memory address is applied which results in the activation of a word line. When activated, the word line couples the data stored within the memory cells of its respective row to the bit lines of the array. In typical DRAM, the coupling of memory cells results in a differential voltage appearing on a bit line (or bit line pair). The differential voltage is amplified by a sense amplifier, resulting in amplified data signals on the bit lines. The applied memory address also activates column decoder circuits, which connect a given group of bit lines to input/output circuits. Commonly, the memory address is multiplexed, with a row address being applied initially to select a word line, and a column address being applied subsequently to select the group of bit lines.
The typical DRAM memory cell stores data by placing charge on, or removing charge from, a storage capacitor. Over time, this charge is reduced by way of a leakage current. Thus, it is important for the DRAM to restore the charge on the capacitor before the amount of charge falls below a critical level, due to leakage mechanisms. Restoration of charge is accomplished with a refresh operation.
The critical level of charge for a storage capacitor is determined by the sensitivity of the memory device sense amplifiers. The storage capacitor must have enough charge to create a sufficient differential voltage for the sense amplifier to reliably sense, without producing an erroneous output. The time needed before the charge on the capacitor falls below the critical level is commonly referred to as the maximum xe2x80x9cpausexe2x80x9d period. A DRAM must perform a refresh operation on every row in the device before that row experiences the maximum xe2x80x9cpausexe2x80x9d period. Read operations and write operations will also serve to refresh the memory cells of a row.
As DRAMs are being used in battery operated applications, such as laptop computers, it is crucial to reduce the power consumed by DRAMs, and thus allow a longer battery lifetime for battery operated systems. Every refresh operation a DRAM must perform consumes a considerable amount of power. This power is wasted because it is not typically performed to transfer data to or from the DRAM for the system""s needs. The refresh operation is used only to sustain the data integrity in the DRAM. Thus, it is important to reduce the number of refresh operations needed over time. One way of achieving this goal is to reduce the rate of charge leakage from the storage capacitor.
To better understand the distinguishing features and advantages of the present invention, a prior art DRAM will be discussed. Referring now to FIG. 1, a DRAM array is set forth and designated by the general reference character 100. The DRAM array 100 is arranged as an nxc3x97m array, having n rows and m columns. The DRAM array 100 includes a word line driver bank 102 coupled to n sets of word lines (WL0-WLn), as well as a sense amplifier bank 104, coupled to m sets of bit line pairs (BL0, BL0_-BLm, BLm_). A memory cell is formed where a word line intersects a bit line pair. The memory cells are designated as M00-Mnm, where the first digit following the xe2x80x9cMxe2x80x9d represents the physical row of the memory cell""s location, and the second digit represents the physical column of the memory cell""s location. For example, M00 is the memory cell located at the intersection of WL0 and bit line pair BL0, BL0_. Each memory cell (M00-Mnm) contains a pass transistor (shown as n-channel MOSFETs Q00-Qnm) and a storage capacitor (shown as C00-Cnm). Each memory cell further includes a storage node 106-112 formed at the junction of the source of the pass transistor (Q00-Qnm) and its associated storage capacitor (C00-Cnm).
The word line driver bank 102 is separated into n separate word line driver circuits shown as DRV0-DRVn. The word line driver bank 102 is responsive to a row address (not shown) such that only one word line driver circuit (DRV0-DRVn) will drive its corresponding word line high according to the row address received. For example, word line driver circuit DRV0 will drive word line WL0 high when the row address value of xe2x80x9czeroxe2x80x9d is received, and word line driver circuit DRVn will drive word line WLn high when the row address value of xe2x80x9cnxe2x80x9d is received.
The sense amplifier bank 104 is separated into m separate sense amplifier circuits, shown as SA0-SAm. For reasons discussed below, while all of the sense amplifiers 104 will be activated simultaneously, only selected of the sense amplifiers in the sense amplifier bank 104 will pass its sensed data to the DRAM output (not shown). A sense amplifier (SA0-SAm) will be selected according to the column address (not shown) applied to a column decoder (also not shown) in the DRAM.
Data is stored in the DRAM array 100 by placing or removing charge from the storage capacitors (C00-Cnm). In a write cycle, a row address is applied to the DRAM and will activate a word line. In this example assume a logic value xe2x80x9c1 xe2x80x9d is to be written into memory cell M00. Word line driver circuit DRV0 within the word line driver bank 102 will raise word line WL0 to a high logic level. A column address will couple write circuitry (not shown) to bit line BL0 to allow a high logic level to be written into storage cell M00. The high logic level will be stored in memory cell M00 at storage node 106 by placing charge on storage capacitor C00. In order to ensure maximum charge is placed on the storage capacitor, word line driver circuit DRV0 will raise word line WL0 to a voltage level that is at least one n-channel threshold voltage (Vtn) above the voltage level applied to bit line BL0 during the write cycle.
Once storage node, 106 reaches a high logic level, which is typically equal to the high power supply voltage (Vcc) of the DRAM array 100, the DRAM is allowed to go into a precharge state in which word line WL0 will be driven to a low logic level, for example the low power supply voltage (Vss). In this state, the storage node 106 will be isolated from the bit line BL0 as the pass transistor Q00 will be in a non-conducting state.
Because the leakage characteristics of the storage capacitor C00 and pass transistors Q00 are not ideal, once the storage node 106 becomes isolated from the bit line BL0, the charge stored on the storage capacitor C00 will leak away, and the voltage will slowly be reduced. As mentioned previously, the charge on the storage capacitor C00 must be restored before the charge level falls below the critical level. This helps to ensure that the data will be reliably sensed by sense amplifier SAo. The data may be restored during either a read operation or a refresh operation, as determined by control signals (not shown) that may be applied to the DRAM. In both cases, the data of a complete row of DRAM cells will be restored.
In order to restore the data in the row formed by word line WL0, word line driver WL0 will be activated, raising word line WL0 at least one Vtn above the DRAM array 100 high power supply voltage Vcc. As a result, the pass transistors connected to word line WL0 are turned on, coupling the storage nodes of the row to their respective bit lines BL0-BLm. This creates a differential voltage across the bit line pairs (BL0, BL0_-BLm, BLm_) having a value that is dependent upon the data stored at the accessed storage nodes. For example, as noted above, storage node 106 has a logic level xe2x80x9c1xe2x80x9d stored on it, thus, bit line BL0 will rise to a potential that is slightly higher than the potential of bit line BL0_at the beginning of the read or refresh cycle. Conversely, if the storage node 106 had stored a logic level of xe2x80x9c0 xe2x80x9d, the bit line BL0 would achieve a lower voltage than bit line BL0_.
Shortly after the differential voltage is achieved on the bit lines (BL0, BL0_-BLm, BLm_), the sense amp bank 104 is activated. When activated, these sense amplifiers (SA0-SAm) xe2x80x9csensexe2x80x9d (amplify) the voltage differential on the bit lines pairs (BL0, BL0_-BLm, BLm_), resulting in an output having a full logic logic level (either Vcc or Vss, depending upon the logic level stored in the memory cell).
Because the pass transistors coupled to word line WL0 are still turned on, the amplifying operation of each sense amplifier (SA0-SAm) will apply complementary full logic levels to its respective bit line pair (BL0, BL0_to BLm, BLm_. In the particular example described herein, because memory cell M00 stores a logic xe2x80x9c1xe2x80x9d, sense amplifier SAo will apply a voltage level of Vcc to bit line BL0 and a voltage of Vss to bit line BL0_. With word line WL0 at a voltage at least one Vtn above Vcc, a full Vcc level will be applied back to the storage node 106. In this manner, the voltage level on the storage node 106 is restored. Likewise, all of the memory cells coupled to word line WL0 will have their data restored to a full logic level (Vcc or Vss in the example of FIG. 1).
As mentioned above, a read or refresh operation must be performed on each row in the DRAM before the charge level on the storage node 106 falls below the critical level. Thus, it is important to make the pass transistor Q00 and storage capacitor C00 as ideal (non-leaky) as possible. Furthermore, the critical charge level is dependent upon the capacitance of the storage capacitor C00: The larger the capacitance, the greater amount of charge that can be stored on the capacitor. Having more charge on the capacitor means that more charge can be lost before the total charge on the capacitor falls below the critical level. Thus, it is important to construct storage capacitors to have as large a capacitance as possible. At the same time, while it is desirable to increase capacitor size, it is also desirable to reduce the overall size of the DRAM.
Referring to FIG. 2, memory cell M00 of FIG. 1 is set forth in a side cross-sectional view. The memory cell M00 is designated by the general reference character 200, and is shown to include a pass transistor 202, and a storage capacitor 204 formed on a substrate 206. The pass transistor 202 couples the storage capacitor 204 to a bit line 208 in order to allow data to be read from, written to, or refreshed in the memory cell 200.
The storage capacitor 204 includes a storage node 210 and a top plate 212 that are separated by a capacitor dielectric 214. The storage node 210 is formed from polysilicon and is coupled to the pass transistor 202. The capacitor dielectric 214 may be silicon dioxide (SiO2). Alternatively, the capacitor dielectric 214 could be a silicon dioxide-silicon nitride-silicon dioxide (SiO2xe2x80x94Si3N4xe2x80x94SiO2) combination, which can increase the capacitance of the capacitor due to the increased dielectric constant properties of the silicon nitride (xe2x80x9cnitridexe2x80x9d) layer. The top plate 212 is formed from polysilicon, and all storage cells on the DRAM array may share the same top plate 212. The top plate 212 may have a voltage equivalent to Vcc/2, to reduce the electric field across the capacitor dielectric 214.
The capacitance of the storage capacitor 204 is determined by the surface area of the storage node 210, the dielectric constant of the capacitor dielectric 214, and the thickness of the capacitor dielectric 214 (the distance between the top plate 212 and the storage node 210). As noted above, while it is desirable to increase the capacitance of the memory cell 200, it is also desirable to do so without increasing the area of the DRAM storage cell, in order to not increase the overall size of the DRAM device.
The pass transistor 202 is shown to include a source region 216 and a drain region 218 formed within the substrate 206. The pass transistor 202 also includes a control gate 220 placed between the source region 216 and drain region 218, and separated from the substrate 206 by a thin control dielectric 222. The substrate 206 is P-type doped monocrystalline silicon and the source region 216 and drain region 218 are N-type doped silicon. The control gate 220 is polysilicon, and the thin control dielectric 222 may be silicon dioxide (xe2x80x9coxidexe2x80x9d), or a combination oxide-nitride layer. The pass transistor 202 is coupled to the storage capacitor 204 via the drain region 218. The pass transistor 202 is further coupled to a bit line contact 224, via the source region 216. The contact 224 is coupled to a bit line 208. The bit line 208 is a metal, for example Al, or alternatively, a titanium-tungsten combination (TiW).
In operation, when the control gate 220 is more than one threshold voltage above the potential of the source region 216, a low impedance path is formed between the storage node 210 and the bit line 208. In this manner, data can be read from, written to, or restored at the storage node 210. However, if the control gate 220 is at a voltage less than the threshold voltage of the pass transistor 202 (with respect to the source region 216), the pass transistor 202 forms a high impedance path between the storage capacitor 204 and the bit line 208. In this manner, the storage node 206 is isolated from the bit line 208, and only unwanted leakage mechanisms may interfere with the data integrity.
One such unwanted leakage mechanism is current leaking from the drain region 218 to the source region 216 of the pass transistor 202. This current is represented by the character xe2x80x9cIleakxe2x80x9d in FIG. 2. The current Ileak can be problematic, due to short channel effects as the distance between the drain region 218 and the source region 216 is reduced. This raises a barrier to the limit to which transistor dimensions can be shrunk, which in turn, places a limitation on how small a DRAM array can be. Short channel effects will further effect the reliability of adjusting the threshold voltage of the pass transistor 202. Because the operation of the pass transistor 202 is dependent upon its threshold, it would be desirable to have greater control over the channel region of the pass transistor 202.
The control gate 220 runs the full length of the DRAM array in the x-direction, forming the word line shown as WL0 in FIG. 1. Referring back to FIG. 1, each word line is shown to be coupled to the control gate of all the DRAM cells in that particular row. This arrangement results in a relatively large capacitive load on the word line. In order to reduce the speed required to drive the word line between high and low voltages, it is desirable to make the word line have as little resistance as possible. As mentioned above, the control gate 212 is made of polysilicon, which has a higher resistance than metal layers. The polysilicon word line resistance may be reduced by forming a self-aligned silicide (salicide) structure on it. Alternatively, a metal layer may run parallel and over the polysilicon, and be periodically connected to the polysilicon by way of contacts. Such a structure is often referred to as a xe2x80x9cstrappedxe2x80x9d word line.
It would be desirable to form a DRAM storage cell with a high storage capacitance and a low amount of charge leakage through the channel region of the pass transistor. Furthermore, it is desirable to do so while maintaining a compact memory cell size, and high speed memory cell and memory cell array performance.
According to the present invention, a dynamic random access memory (DRAM) cell includes a pass transistor and a charge storage device. The pass transistor is double-gated, having both a top gate and a bottom gate. The double-gate structure provides greater control over the channel region, resulting in advantageous charge storage capabilities. In addition, the double-gate structure allows for shorter channel dimensions, improving the density of DRAM arrays employing the preferred embodiment memory cell.
According to one aspect of the preferred embodiment, the DRAM cell pass transistor is a silicon-on-insulator device.
According to another aspect of the preferred embodiment, the DRAM cell pass transistor is isolated from adjacent devices by etching a silicon layer to form active area silicon mesas.
According to another aspect of the preferred embodiment, the DRAM cell includes a stacked capacitor.
An advantage of the preferred embodiment is that it provides a DRAM cell having low leakage characteristics and reduced silicon area. dr
FIG. 1 is a block schematic diagram of a prior art DRAM array.
FIG. 2 is a side cross-sectional view of a prior art DRAM memory cell.
FIG. 3 is a side cross-sectional view illustrating a DRAM memory cell according to a preferred embodiment.
FIG. 4 is a block schematic diagram illustrating a DRAM array according to the preferred embodiment.
FIG. 5 is a schematic diagram of a memory cell of the preferred embodiment DRAM array of FIG. 4.
FIG. 6 is a schematic diagram of a word line strap structure of the preferred embodiment DRAM array of FIG. 4.